Conventionally, in a chip set such as a system-on-chip (hereinafter referred to as “SoC (System on Chip)”) in which a critical word first (hereinafter referred to as “CWF (Critical Word First)”) compatible bus and a CWF incompatible bus coexist, when data requested by a processing unit connected to the CWF compatible bus is stored in a main memory such as a DRAM (Dynamic Random Access Memory) connected to the CWF incompatible bus, the data is transferred from the main memory to the processing unit via the CWF incompatible bus.
However, data that the processing unit will process (hereinafter referred to “critical word”) is included at a random position in the data transferred from the main memory. In this case, the processing unit remains on a stall state until the processing unit receives the critical word. As a result, the processing efficiency of the processing unit decreases.
Conventionally, it is desired to improve the processing efficiency of the processing unit when data is transferred from the main memory connected to the CWF incompatible bus to the processing unit connected to the CWF compatible bus.